60% Keyboard Kit

I have been using 60% keyboard. For some years, it was my practice buying a kit (of GH60 variant) around end of year (with Aliexpress or Taobao) and building it in new year.

Basically …

Running the RNG to evaluate the output

In the Gomti collection, there are a few Verilog implementations for multiple targets. Currently, those implementations are under evaluation.

The RNG is "bare" version, with no conditioning component. That is, in the actual use case, it is assumed that adding conditioning component after …

Asynchronous RNG output

The first and the second entries are designed in a way that all components are clocked by CLK. These ones are straightforward. However, the parameter Kd can be even, which results sensitivity to jitter bad.

Another variant is possible, to allow Kd can be odd. It is …

Use of XOR accumulator

I draw another schematics, the main part is like following.

Instead of a shift register and a set of xor gates, it only uses an accumulator and a single xor gate.

The shift register was used because I had an idea of changing the shift register …