GNU wannabee and Happy Hacking
In the Gomti collection, there are a few Verilog implementations for multiple targets. Currently, those implementations are under evaluation.
The RNG is "bare" version, with no conditioning component. That is, in the actual use case, it is assumed that adding conditioning component after …
The first and the second entries are designed in a way that all components are clocked by CLK. These ones are straightforward. However, the parameter Kd can be even, which results sensitivity to jitter bad.
Another variant is possible, to allow Kd can be odd. It is …
I draw another schematics, the main part is like following.
Instead of a shift register and a set of xor gates, it only uses an accumulator and a single xor gate.
The shift register was used because I had an idea of changing the shift register …
I start a project, named Gomti. It's a collection of configurations and implementations to build a PLL-based true random number generater (TRNG). The central part of Gomti is actually, curated rational numbers to build PLL RNG.
The name "gomti" is an acronym to remember the first part of …