Asynchronous RNG output

The first and the second entries are designed in a way that all components are clocked by CLK. These ones are straightforward. However, the parameter Kd can be even, which results sensitivity to jitter bad.

Another variant is possible, to allow Kd can be odd. It is "asynchronous RNG output" design. In the design, there are two different clock domains:

• CLK: the RNG component
• CLJ: other compnents

The RNG output is handled by components with different clock domain.

Third entry: a192-192-425 for GW1NR-9

The third entry is: 192/425 for TEC0117. That is,

• Target FPGA is GW1NR-9.
• CLK = 425MHz
• CLJ = 192MHz
• Generation speed: 1Mbps
• CLJ clock is 192MHz (so that we can build USB function with 48MHz).

Forth entry: a192-256-567 for GW1NR-9C

The forth entry is: 256/567 for Tang Nano 9K. That is,

• Target FPGA is GW1NR-9C.
• CLK = 425.25MHz
• CLJ = 192MHz
• Generation speed: 0.75Mbps
• CLJ clock is 192MHz (so that we can build USB function with 48MHz).
• Using 27MHz clock input of Tang Nano 9K

Fifth entry: a240-112-125 for iCE40 HX8K

The fifth entry is: 112/125 for iCE40 HX8K. That is,

• Target FPGA is iCE40 HX8K.
• CLK = 267.857MHz
• CLJ = 240MHz
• Generation speed: 2+1/7 Mbps
• CLJ clock is 240MHz (so that we can build USB function with 48MHz).