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NIIBE Yutaka's glog, Eight disks, three pegs, and just a little hack.

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• Towers of Hanoi
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GNU GPL LED Display
At GPLv3 conference, Gniibe presented the talk on "GNU GPL LED Display" along with Japanese situation on Free Software.

GNU GPL LED Display is a gadget which displays GNU GPLv3 (draft) on its 32x16 led dot matrix.

[/verilog] permanent link

My First Verilog
Today, I've installed 'verilog' (Icarus Verilog) on my machine.

Here is my first verilog.

`timescale 1ps/1ps

module fulladd(A, B, CIN, Q, COUT);
input A,B,CIN;
output Q, COUT;

assign Q = A^B^CIN;
assign COUT = (A&B) | (B&CIN) | (CIN&A);
endmodule 


module adder(a,b,q);
input [3:0] a,b;
output [3:0] q;
wire [3:0] cout;

fulladd add0 (  .Q(q[0]), .COUT(cout[0]),
	     .A(a[0]), .B(b[0]), .CIN (1'b0));
fulladd add1 (  .Q(q[1]), .COUT(cout[1]),
	     .A(a[1]), .B(b[1]), .CIN (cout[0]));
fulladd add2 (  .Q(q[2]), .COUT(cout[2]),
	     .A(a[2]), .B(b[2]), .CIN (cout[1]));
fulladd add3 (  .Q(q[3]), .COUT(cout[3]),
	     .A(a[3]), .B(b[3]), .CIN (cout[2]));

endmodule

module adder_tp;
reg [3:0] a, b;
wire [3:0] q;
parameter STEP = 100000;

adder adder(a, b, q);

initial begin
	a = 4'h0; b= 4'h0;
  #STEP	a = 4'h5; b= 4'ha;
  #STEP	a = 4'h7; b= 4'ha;
  #STEP	a = 4'h1; b= 4'hf;
  #STEP	a = 4'hf; b= 4'hf;
  #STEP	$finish;
end

initial $monitor( $stime, " a=%h b=%h q=%h", a, b, q);

endmodule

$ ./a.out
                   0 a=0 b=0 q=0
              100000 a=5 b=a q=f
              200000 a=7 b=a q=1
              300000 a=1 b=f q=0
              400000 a=f b=f q=e

[/verilog] permanent link